High performance analog signal processing systems often operate on ratios of analog signals. Operating on such ratios offers these systems freedom from certain errors which relate to the absolute scale of the analog signal being processed. It is also often desirable to apply a known gain to at least one of the signals in a ratio, for example to allow processing of this signal with reduced or eliminated concern for error sources with fixed absolute scale, such as noise.
One common example of such a system is an analog-to-digital converter (ADC). The function of an ADC is to produce a digital output signal as a function of an analog input signal (for example a voltage) as it relates to a reference signal.
A known technique for accomplishing this function is to generate the digital output signal using a multi-stage ADC. Such an ADC includes at least one stage comprising an ADC of lower resolution than the overall converter resolution. The stage quantizes an analog input, and a digital-to-analog converter (DAC) produces an analog representation of the ADC output. An analog subtraction unit produces a residue signal. The residue signal is the difference between the analog input and the output of the DAC. The residue is then amplified and processed by additional, similarly constructed stages, the last of which produces the least significant bit, and may dispense with the DAC and subtraction unit.
An example of an application employing this technique is shown in block-diagram form as 100 in FIG. 1. The illustrated device is shown as a three stage converter. One stage includes ADC 102, DAC 102 and subtraction unit 106, while a second stage includes ADC 112, DAC 114, and subtraction 116. The last stage only includes ADC 122 since no residue unit is required. Interstage amplifiers 110 and 120 amplify the residues produced by the first stages prior to being presented to the next stage. The final converter result is produced by combining the individual ADC digital outputs 103, 113, and 123.
The multistage architecture offers the advantage that the individual ADCs and DACs may have dramatically coarser resolution than the overall converter resolution, resulting in a commensurate decrease in overall converter size and complexity, and therefore typically an increase in speed and decrease in power. Furthermore, the interstage amplifiers may incorporate sample-and-hold (S/H) circuitry to form a pipeline converter, which allows the first stage to begin processing an input sample while later stages are still occupied processing previous input sample(s).
While the multistage architecture reduces the resolution requirements of the components in each of the stages, the accuracy (including noise and linearity effects) requirements are more stringent. In particular, the residue presented to the second stage must be accurate to the full resolution of the converter, implying that DAC 104, subtractor 106 and amplifier 110 need to be similarly accurate in order to insure that the residue provided by one stage and applied to the next will not introduce errors going forward in the succession of stages.
This requirement necessitates tradeoffs in the design of the interstage amplifiers which tend to degrade system performance. The gain of the amplifiers (A1 and A2 respectively for amplifiers 110 and 120) is required to be accurate so that the relative weights of bits in all of the ADCs and DACs are well correlated with respect to the input signal and the reference signal. In practice, this leads to closed-loop solutions using operational amplifiers or similar circuits which derive their accuracy from feedback networks and high open-loop gains. The stability requirements of these closed-loop systems in turn limit the speed, noise, and power performance of the amplifiers, and thereby the ADC as a whole.